-- MAX+plus II VHDL Template

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_ARITH.all;
USE ieee.std_logic_unsigned.all;

ENTITY reg8_1 IS

PORT
(
clk,ldn,clrn: IN bit;
dsr: in STD_LOGIC;
D: in STD_LOGIC_vector(7 downto 0);
Q: out STD_LOGIC_vector(7 downto 0)

);

END reg8_1;

ARCHITECTURE a1 OF reg8_1 IS

signal sreg8: STD_LOGIC_vector(7 downto 0);

BEGIN

process(clrn,clk,ldn,d)
begin
if clrn='0' then sreg8 <= "00000000"; else

if clk'event and clk='1' then
if ldn='0' then sreg8<=d;
else sreg8(6 downto 0)<=sreg8(7 downto 1);
sreg8(7)<=dsr;
end if;
end if;
end if;
q<=sreg8;

end process;
END a1;